Nonvolatile semiconductor memory device
US8576606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Sep 26, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.