Matrix multiplication operations with data pre-conditioning in a high performance computing architecture
US8577950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2009 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.