System and method for aligning change-of-flow instructions in an instruction buffer
US8578134B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2005 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Jun 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30149
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and processor are provided. The method includes storing a first value at a first field of a first cache tag line when a next occurrence of a first COF instruction is presumed to branch and when the end location of the first COF instruction is at a first location of memory, storing a second value at the first field to indicate the next occurrence of the first COF instruction is presumed to branch and when the end location of the first COF instruction is at a second location of memory. The processor includes an instruction cache having instruction data represented by a plurality of data segments and a prefetch unit. The prefetch unit is operable to receive a first data segment from the instruction cache and determine whether an end byte of a predicted taken COF instruction is present in the first data segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.