Method for manufacturing a semiconductor device with gate spacer
US8580633B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
Abstract
A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a gate disposed over a semiconductor substrate; a first spacer disposed over sidewalls of the gate; an insulating layer pattern disposed over sidewalls of the first spacer; and a second spacer disposed over the first spacer and the insulating pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.