3D memory semiconductor device and structure
US8581349B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Oct 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.