Integrated circuit having a semiconductor substrate with barrier layer

US8581405B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Qimonda AG · DE

Inventors

• Stephan Dertinger · Tokyo, JP
• Alfred Martin · Munich, DE
• Barbara Hasler · Munich, DE
• Grit Sommer · Grafing, DE
• Florian Binder · Traunstein, DE

Key dates

• Filing date: Jun 2, 2011
• Grant date: Nov 12, 2013
• Expiry date: Jun 2, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0335
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.