Evaluating routing congestion based on average global edge congestion histograms
US8584070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.