Method of making a semiconductor device
US8586478B2 · kind B2 · utility
14Cited by
3References
13Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 20, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Mar 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.