Integrated circuit and fabricating method thereof
US8587078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2010 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2031 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0771
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.