Patent · US Active

Global bit line restore by most significant bit of an address line

US8587990B2 · kind B2 · utility

2Cited by

4References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yuen H. Chan · Poughkeepsie, US
Michael Kugel · Eppelheim, DE
Raphael Polig · Dietikon, CH
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Jul 11, 2011
Grant date	Nov 19, 2013
Priority date	—
Expiry date	Jan 10, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.