Balanced on-die termination
US8588012B2 · kind B2 · utility
28Cited by
30References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2011 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jan 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.