Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals
US8589662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Feb 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.