Reducing power consumption in clock and data recovery systems
US8589708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Apr 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.