Patent · US Active

Error tolerant flip-flops

US8589775B2 · kind B2 · utility

1Cited by

2References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Georg Georgakos · Fraunberg, DE
Michael Goessel · Roter Dudel, DE
Anton Huber · Burghausen, DE

Key dates

Filing date	Mar 14, 2011
Grant date	Nov 19, 2013
Priority date	—
Expiry date	Jan 18, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0411
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.