Architectural physical synthesis

US8589850B2 · kind B2 · utility

Assignee

• SYNOPSYS, INC. · US

Inventors

• Kenneth S. McElvain · Los Altos, US
• Benoit Lemonnier · Palo Alto, US
• William Halpin · Palo Alto, US

Key dates

• Filing date: Jul 22, 2008
• Grant date: Nov 19, 2013
• Expiry date: Oct 21, 2030

Classification

• Technology area (CPC —): General

Abstract

The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.