Wafer and method of processing wafer
US8592297B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.