Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8592872B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.