Network on chip building bricks
US8593818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Jul 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick. The bricks are oriented at 180° from one to the next in the direction of the columns and in the direction of the rows, and each brick comprises an even number of power supply conductor segments arranged symmetrically with respect to an axis of symmetry of the brick and conne…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.