System and method for performing dynamic mixed mode read validation in a software transactional memory
US8595446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Sep 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The transactional memory system described herein may apply a mix of read validation techniques to validate read operations (e.g., invisible reads and/or semi-visible reads) in different transactions, or to validate different read operations within a single transaction (including reads of the same location). The system may include mechanisms to dynamically determine that a read validation technique should be replaced by a different technique for reads of particular locations or for all subsequent reads, and/or to dynamically adjust the balance between different read validation techniques to manage costs. Some of the read validation techniques may be supported by hardware transactional memory (HTM). The system may delay acquisition of ownership records for reading, and may acquire two or more ownership records back-to-back (e.g., within a single hardware transaction). The user code of a software transaction may be divided into multiple segments, some of which may be executed within a hardware transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.