Inventor · Cambridge, MA, US

Yosef Lev

46Patents
9h-index
23Co-inventors
75Inventor score

Filing activity: Nov 5, 2004 → Nov 20, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7516366B2 System and method for executing nested atomic blocks using split hardware transactions Physics 67 Active
US8316352B2 Watchpoints on transactional variables Physics 39 Active
US8966491B2 System and method for implementing NUMA-aware reader-writer locks Physics 22 Active
US7711909B1 Read sharing using global conflict indication and semi-transparent reading in a transactional memory space Physics 20 Active
US7849446B2 Replay debugging Physics 16 Active
US7346753B2 Dynamic circular work-stealing deque Physics 15 Expired
US8307346B2 Atomic groups for debugging Physics 10 Active
US9043363B2 System and method for performing memory management using hardware transactions Physics 10 Active
US7516365B2 System and method for split hardware transactions Physics 9 Active
US8117605B2 Method and apparatus for improving transactional memory interactions by tracking object visibility Physics 9 Active
US7840947B2 Delayed breakpoints Physics 7 Active
US8918596B2 System and method for implementing NUMA-aware statistics counters Physics 6 Active
US8332374B2 Efficient implicit privatization of transactional memory Physics 6 Active
US7620850B2 Breakpoints in a transactional memory-based representation of code Physics 5 Active
US7921407B2 System and method for supporting multiple alternative methods for executing transactions Physics 4 Active
US10055129B2 Read concurrency using hardware transactional lock elision Physics 4 Active
US9317339B2 Systems and methods for implementing work stealing using a configurable separation of stealable and non-stealable work items Physics 4 Active
US8504540B2 Scalable reader-writer lock Physics 3 Active
US7779222B1 Dynamic memory work-stealing Physics 3 Expired
US7363438B1 Extendable memory work-stealing Physics 3 Expired
US9727369B2 System and method for implementing reader-writer locks using hardware transactional memory Physics 3 Active
US8595446B2 System and method for performing dynamic mixed mode read validation in a software transactional memory Physics 3 Active
US9342380B2 System and method for implementing reader-writer locks using hardware transactional memory Physics 3 Active
US8181158B2 Viewing and modifying transactional variables Physics 3 Active
US9183048B2 System and method for implementing scalable contention-adaptive statistics counters Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.