Method and apparatus of forming ESD protection device
US8598656B2 · kind B2 · utility
6Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.