Ming Zhu
131Patents
11h-index
70Co-inventors
79Inventor score
Filing activity: Dec 29, 2004 → Jun 16, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8586436B2 | Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device | Electricity | 44 | Active |
| US8754470B1 | Vertical tunneling field-effect transistor cell and fabricating the same | Electricity | 39 | Active |
| US8557659B2 | Spacer structures of a semiconductor device | Electricity | 20 | Active |
| US8183644B1 | Metal gate structure of a CMOS semiconductor device | Electricity | 19 | Active |
| USD539290S1 | Stand for computer enclosure | General | 18 | Expired |
| US8368127B2 | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current | Electricity | 18 | Active |
| US8742492B2 | Device with a vertical gate structure | Electricity | 15 | Active |
| US9583499B1 | Devices with embedded non-volatile memory and metal gates and methods for fabricating the same | Electricity | 15 | Active |
| US8304831B2 | Method and apparatus of forming a gate | Electricity | 14 | Active |
| US8614484B2 | High voltage device with partial silicon germanium epi source/drain | Electricity | 14 | Active |
| US8349678B2 | Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain | Electricity | 13 | Active |
| US8304840B2 | Spacer structures of a semiconductor device | Electricity | 8 | Active |
| US8703595B2 | N/P boundary effect reduction for metal gate transistors | Electricity | 8 | Active |
| US8450216B2 | Contact etch stop layers of a field effect transistor | Electricity | 7 | Active |
| US9595443B2 | Metal gate structure of a semiconductor device | Electricity | 7 | Active |
| US9219124B2 | Metal gate semiconductor device | Electricity | 7 | Active |
| USD517075S1 | Computer front bezel | General | 7 | Expired |
| US9111780B2 | Structure and method for vertical tunneling field effect transistor with leveled source and drain | Electricity | 7 | Active |
| US8969949B2 | Structure and method for static random access memory device of vertical tunneling field effect transistor | Electricity | 7 | Active |
| US8304842B2 | Interconnection structure for N/P metal gates | Electricity | 7 | Active |
| US8835294B2 | Method for improving thermal stability of metal gate | Electricity | 7 | Active |
| US8592945B2 | Large dimension device and method of manufacturing same in gate last process | Electricity | 6 | Active |
| US8598656B2 | Method and apparatus of forming ESD protection device | Electricity | 6 | Active |
| US8889501B2 | Methods for forming MOS devices with raised source/drain regions | Electricity | 6 | Active |
| US9190484B2 | Vertical tunneling field-effect transistor cell and fabricating the same | Electricity | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.