Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process

US8598678B2 · kind B2 · utility

Assignee

• SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD. · CN

Inventors

• Wensheng Qian · Shanghai, CN
• Jun Hu · Shanghai, CN
• Donghua Liu · Shanghai, CN

Key dates

• Filing date: Dec 8, 2010
• Grant date: Dec 3, 2013
• Expiry date: Dec 6, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/401

Abstract

A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.