Built in system bus interface for random access to programmable logic registers
US8598908B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to provide random access to a programmable logic register. A processing device in a programmable logic system retrieves data from a memory of the programmable logic system. The data is loaded into a configuration register configured to store configuration data for a programmable logic function over a system bus. The processing device programs a programmable logic block to implement the programmable logic function based on the configuration data, where the processing device is configured to access a first configuration register in the configuration register set, the first configuration register corresponding to a first programmable logic block in the programmable logic system, without affecting a second configuration register corresponding to a second programmable logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.