Phase locked loop with adaptive loop filter
US8598955B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.