Computing tessellation coordinates using dedicated hardware
US8599202B1 · kind B1 · utility
11Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.