Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus
US8599886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.