Speculation-aware memory controller arbiter
US8601221B2 · kind B2 · utility
8Cited by
6References
7Claims
0Family size
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Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory arbiter minimizes latency of memory accesses in a system having multiple processors. The memory arbiter improves overall system performance by managing the memory requests from each processor individually before those requests are sent to a central memory arbiter for handling memory requests for the shared resources from the multiple processors. The local memory arbiter buffers the memory requests from a local processor, analyzes the buffered memory requests, and optimizes the requests by reordering commands according to a rule set, and by performing write merging and prefetch squashing in certain conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.