Patent · US Active

Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiP

US8601422B2 · kind B2 · utility

1Cited by

4References

22Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Alok Tripathi · Beaverton, US
Abha Jain · San Jose, US
Parag Choudhary · Noida, IN
Utpal Bhattacharya · Noida, IN

Key dates

Filing date	Dec 22, 2008
Grant date	Dec 3, 2013
Priority date	—
Expiry date	Sep 30, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.