Bias compensation method and system for minimizing process, voltage and temperature corner variations
US8604826B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.