Frequency synthesizer noise reduction
US8604840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2009 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Oct 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (ΔI). The current array is biased by the reference bias current. The down modification signal (ΔI) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.