Semiconductor device having hierarchical structured bit line
US8605476B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.