System and method for testing for defects in a semiconductor memory array
US8605525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jan 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.