Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods
US8605536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.