Hierarchical bottom-up clock domain crossing verification
US8607173B2 · kind B2 · utility
3Cited by
16References
12Claims
0Family size
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Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.