Wafer level packaged focal plane array
US8608894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A method for manufacturing a wafer level packaged focal plane array, in accordance with certain embodiments, includes forming a detector wafer, which may include forming detector arrays and read-out circuits. The method may also include forming a lid wafer. Forming the lid wafer may include polishing a surface of a magnetically confined Czochralski (MCZ) wafer, bonding a Czochralski wafer to the MCZ wafer, and forming pockets in the Czochralski wafer. Each pocked may expose a portion of the polished surface of the MCZ wafer. The method may further include bonding the lid wafer and the detector wafer together such that the each detector array and read-out circuit are sealed within a different pocket, thereby forming a plurality of wafer level packaged focal plane arrays. The method may additionally include separating at least one wafer level packaged focal plan array from the plurality of wafer level packaged focal plane arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.