Cap and substrate electrical connection at wafer level
US8609466B2 · kind B2 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2009 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Sep 14, 2029 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0118
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A cap and substrate having an electrical connection at a wafer level includes providing a substrate and forming an electrically conductive ground structure in the substrate and electrically coupled to the substrate. An electrically conductive path to the ground structure is formed in the substrate. A top cap is then provided, wherein the top cap includes an electrically conductive surface. The top cap is bonded to the substrate so that the electrically conductive surface of the top cap is electrically coupled to the path to the ground structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.