Surround gate CMOS semiconductor device
US8609494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2013 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.