Method of dual EPI process for semiconductor device
US8609497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2010 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Dec 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
Abstract
The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.