3D via capacitor with a floating conductive plate for improved reliability
US8609504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.