Method for forming a three-dimensional structure of metal-insulator-metal type
US8609530B2 · kind B2 · utility
1Cited by
2References
8Claims
0Family size
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Key dates
| Filing date | Mar 21, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Oct 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.