Integrated circuit decoupling capacitor arrangement
US8610188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Sep 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.