Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active regions
US8610192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.