Split-gate lateral diffused metal oxide semiconductor device
US8610206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.