Integrated circuit with multi recessed shallow trench isolation
US8610240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2010 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.