Integrated circuit
US8610475B2 · kind B2 · utility
6Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2010 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.