Circuit for preventing a dummy read in a memory
US8611162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.