Multi-layer time-interleaved analog-to-digital convertor (ADC)
US8611483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2012 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.