Identifying logic blocks in a synthesized logic design that have specified inputs
US8612909B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2012 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic blocks in a synthesized logic design that have specified inputs are identified by performing a two-pass analysis of the synthesized logic design. A number of levels is specified. A forward linear trace is performed to identify inputs at each level for each logic block, without regard to the specific function of each logic block. A list of potential equivalency points is generated from the forward linear trace. A reverse logical trace is then performed from the potential equivalency points to identify equivalent logic. When no equivalent logic exists, the analysis can specify one or more additional inputs, or one or more missing inputs, to determine whether similar logic exists that could be replicated and modified to achieve the desired function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.