Self-aligned static random access memory (SRAM) on metal gate
US8614131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2009 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.